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Registration
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Steering Committee
Alan Berenbaum, SMSC
Patrick Crowley, Washington Univ. St. Louis
Mark Franklin, Washington Univ. St. Louis
Haldun Hadimioglu, Polytechnic Univ.
Nick McKeown, Stanford Univ.
Peter Z. Onufryk, IDT
K. K. Ramakrishnan, AT&T Labs
General Chair
Alan Berenbaum, SMSC
Program Chairs
Kai Li, Princeton University
Jonathan Turner, Washington Univ. St. Louis
Finance
Brad Calder, UC San Diego
Tutorials
Erik Johnson, Intel
Local Arrangements
Li-Shiuan Peh, Princeton University
Registration
Qin Lv, Princeton University
Publicity
and Publications
Greg Byrd, NC State University
Program
Committee
Andrew Campbell, Columbia Univ.
Patrick Crowley, Wash. U. St. Louis
Cezary Dubnicki, NEC
Hans Eberle, Sun Microsystems
Dirk Grunwald, Univ. Of Colorado
Roch Guerin, Univ. of Pennsylvania
T.V. Lakshman, Bell Labs
Dan Lenoski, Cisco Systems
Bill Mangione-Smith, UCLA
Kenneth Mackenzie, Reservoir Labs
Nick McKeown, Stanford Univ.
Peter Onufryk, IDT
Li-Shiuan Peh, Princeton Univ.
Mohammad Peyravian, IBM
Henning Schulzrinne, Columbia U.
Steve Scott, Cray
Dimitrious Stiliadis, Bell Labs
Ion Stoica, UC Berkeley
Chuck Thacker, Microsoft
Harrick Vin, UT Austin
Tilman Wolf, UM Amherst
Raj Yavatkar, Intel
Hui Zhang, CMU |
Keynote
Addresses
| Keynote
1: October 27 |
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The
Push of Network Processing to the Top of the Pyramid
Will Eatherton, Cisco Systems
With the shipment
of the Carrier Routing System (CRS-1) by Cisco and the Silicon Packet
Processor (SPP) device inside it, network processors now extend
to the very high end of router systems. This talk will cover the
architecture of the SPP as well as some of the trade-offs and challenges
involved with its development. Additionally, the future challenges
and requirements of network processing in router systems will be
discussed.
Speaker:
Will Eatherton joined Cisco in 2000 with the acquisition
of Growth Networks, where he was one of the founding engineers.
Will’s first contribution at Cisco was his role as the line
card architect for HFR (known officially as the Carrier Routing
System (CRS-1), a scalable multi-terabit router system), where he
also led architecture of the Silicon Packet Processor, (SPP), the
highest performance network processor in the industry today. Will
now is lead architect for a centralized group (that he helped found)
developing next generation packet processing technology for use
across a range of Cisco platforms. Will has 20 patents and is considered
an expert at Cisco on router datapath architecture, classification,
network processors, and memory technology. Will has been a Cisco
Distinguished Engineer since January of 2005. |
| Keynote
2: October 28 |
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Network
Acceleration: Taking Intel Architecture a Step Forward
Hugh Wilkinson, Intel Corporation
Speaker:
Hugh Wilkinson is a Senior Principal Engineer in Intel’s Digital
Enterprise Group. For the last six years, he has been working on
NPU architecture (IXP2800 family) within Intel. In addition, he
has been working on fabric solutions for those NPUs (Advanced Switching
Interconnect). Most recently, he has been working on making IA processors
more effective in communication applications. Prior to working for
Intel, he worked at Digital Equipment Corporation for 18 years,
where he was the technical lead for terminal server products and
subsequently IP switching products. He received a BS in Computer
Science from Boston University.
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