vars.h

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#ifndef VARS_H
#define VARS_H

#include "misc.h"
#include "instr.h"
// #include "nodes.h"

// #include "my_stream.h"
// #include "vis.h"

#define IS_ARG_REG(x) (arch==AVR)?  ((x>=14) && (x<=25)) : \
 (((x>=16) && (x<=21)) || ((x>=48) && (x<=53)))


class CVarRef {
  // Reference to a variable
  CInstr * Instr;
  CVarRef * Next;
 public:
  CVarRef() { Instr = NULL; Next = NULL; };
  CVarRef(CInstr * instr) { assert(instr); Instr = instr; Next = NULL; };
  CVarRef * Get_Next() { return(Next); };
  void Set_Next(CVarRef * next) { Next = next; };
  void Add_VarRef(CInstr * instr);
  
  CInstr * Get_Instr() { return(Instr); };
  void Set_Instr(CInstr * instr) { assert(instr); Instr = instr; };
  
  bool Contains_Pseudo_Instr() {
    CVarRef * cur=this;
    while (cur) {
      if (cur->Instr->Is_Pseudo())
    return true;
      else
    cur = cur->Next;
    }
    return false;
  };
};

class CCDGNode;

class CReg {
  int Reg[FINAL+1];
  int Status;
 public:
  CReg();
  int Get_Status() { return Status; };
  int Get_Number(int which=LATEST);
  void Set_Number(int reg, int which=LATEST);
};

class CVar;

class CVarList {
    CVar * Var;
    CVarList * Next;
public: 
    CVarList() { Var = NULL; Next = NULL; };
    CVarList(CVar * var) { Var = var; Next = NULL; };
    CVar * Get_Var() { return Var; };
    CVarList * Get_Next() { return Next; };
    CVarList * Add_Var(CVar * var);
    bool Contains(CVar * var);
    bool Contains_Alias(CVar * var);
    CVar * Look_Up(int reg);
    int Get_Length();
    void Output_Debug(ostream &stream); 
    void Output_RegNumber_List(ostream &stream);
    bool Replace_All(CVar * old_var, CVar * new_var);
};

class CProc;

class CVar {
    CVarRef * Defs, * Uses;
    CReg Register;
    bool Live;
    CVar * Next, * Prev;
    int VarNumber;
    CVarList InterfEdges;
    CProc * Procedure;
public:
    CVar();
    CVar(int reg);
    void Analyze_Instruction(CInstr * instr, CCDGNode * node);
    void Add_Use(CInstr * instr) { Uses->Add_VarRef(instr); };
    void Add_Def(CInstr * instr) { Defs->Add_VarRef(instr); };
    CVar * Find_Latest_Var(int reg);
    CVar * Find_Next_Var(int reg, int which);
    CVar * Add_Var(CInstr * instr, int reg, int acc_type, int which_acc);

    CReg * Get_Register() { return &Register; };
    int Get_RegNumber(int which=LATEST) { 
      return Register.Get_Number((reg_reallocation_method==NONE)? ORIGINAL : which); 
    };

    CVarRef * Get_Defs() { return Defs; };
    CVarRef * Get_Uses() { return Uses; };
    CVar * Get_Next() { return Next; };
    CVar * Get_Prev() { return Prev; };
    void Set_Next(CVar * next) { Next = next; };
    void Set_Prev(CVar * prev) { Prev = prev; };

    CVar * Merge_Vars(CVar * that);

    int Number_Vars();
    int Get_VarNumber() { return VarNumber; };
    void Virtualize_Registers();
    int Merge_Zero_Register();

    void Find_Interference(int which);
    void Find_InterfEdges(int which);
    CVarList * Get_InterfEdges() { return &InterfEdges; };
    bool Interferes_With(CVar * var) {  
        assert(InterfEdges.Get_Var());
        return InterfEdges.Contains(var); 
    };

    void Output_Debug(ostream &stream, bool show_interference=false);
};

#endif

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