Suleyman Sair's Publications

Here is a current list of my publications while at Northeastern University, UCSD and NCSU, sorted by date, most recent first.

  1. Fei Gao, Hanyu Cui and Suleyman Sair. "Two-level Data Prefetching". In The International Conference of Computer Design (ICCD), October 2007.

  2. Anahita Shayesteh, Glenn Reinman, Norman Jouppi, Suleyman Sair and Timothy Sherwood. "Improving Performance of Shared Helpers in CMP". In The International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2006.

  3. Fei Gao and Suleyman Sair. "Long-term Performance Bottleneck Analysis and Prediction". In The International Conference of Computer Design (ICCD), October 2006.

  4. Eren Kursun, Anahita Shayesteh, Suleyman Sair, Tim Sherwood and Glenn Reinman. "An Evaluation of Deeply Decoupled Cores". In The Journal of Instruction-Level Parallelism, vol. 8, February 2006 (pdf).

  5. Anahita Shayesteh, Glenn Reinman, Norm Jouppi, Suleyman Sair, and Tim Sherwood. "Dynamically Configurable Shared CMP Helper Engines for Improved Performance". In Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP.05) held in conjunction with the 38th Annual International Symposium on Microarchitecture, Nov 2005.

  6. Eren Kursun, Anahita Shayesteh, Suleyman Sair, Tim Sherwood, and Glenn Reinman. "Low-overhead activity migration". In ICCD'05: Proceedings of the International Conference on Computer Design, October 2005.

  7. Youngsoo Kim and Suleyman Sair. "Designing real-time h.264 decoders with dataflow architectures". In CODES+ISSS'05: IEEE/ACM/IFIP International Conference on Hardware - Software Co-design and System Synthesis, September 2005.

  8. Fei Gao and Suleyman Sair. "Exploiting Intra-function Correlation with the Global History Stack". In IEEE Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS V).

  9. Brad Calder, Todd Austin, Don Yang, Timothy Sherwood, Suleyman Sair, David Newquist and Tim Cusac. "BitRaker Anvil: Binary Instrumentation for Rapid Creation of Simulation and Workload Analysis Tools". In Proceedings of Global Signal Processing (GSPx), September, 2004.

  10. Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Tim Sherwood. "Low-Overhead Core Swapping for Thermal Management". Workshop on Power-Aware Computer Systems, 2004. In conjunction with Micro-37, Portland, OR.

  11. Satish Narayanasamy, Yuanfang Hu, Suleyman Sair and Brad Calder. "Converged Trace Schedules for In-Order Processors". In the Proceedings of the Tenth International Symposium on High Performance Computer Architecture, February 2004, Madrid Spain. (pdf)

  12. Timothy Sherwood, Erez Perelman, Greg Hamerly, Suleyman Sair, and Brad Calder. "Discovering and Exploiting Program Phases". IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, Nov./Dec. 2003.

  13. Timothy Sherwood, Suleyman Sair, and Brad Calder."Phase Tracking and Prediction". In the Proceedings of the 30th International Symposium on Computer Architecture, June 2003, San Diego, CA. (pdf)

  14. Suleyman Sair, Timothy Sherwood and Brad Calder. "A Decoupled Predictor-Directed Stream Prefetching Architecture." In IEEE Transactions on Computers, March 2003, Vol 52, No 3. Please email me for a copy (myemailaddress).

  15. Satish Narayanasamy, Tim Sherwood, Suleyman Sair, Brad Calder and George Varghese."Catching Accurate Profiles in Hardware." In the Proceedings of the Ninth International Symposium on High Performance Computer Architecture, February 2003, Anaheim, CA. (pdf)

  16. Jamison Collins, Suleyman Sair, Brad Calder and Dean Tullsen."Pointer Cache Assisted Prefetching." In the Proceedings of the 35th International Symposium on Microarchitecture, November 2002, Istanbul, Turkey. (ps - pdf)

  17. Suleyman Sair, Timothy Sherwood and Brad Calder. "Quantifying Load Stream Behavior." In the Proceedings of the 8th International Symposium on High-Performance Computer Architecture, February 2002, Boston, MA. (ps – pdf)

  18. Timothy Sherwood, Suleyman Sair and Brad Calder. "Predictor-Directed Streaming Buffers." In the Proceedings of the 33rd International Symposium on Microarchitecture, December 2000, Monterey, CA. (ps –pdf)

  19. Suleyman Sair and Mark Charney. "Memory Behavior of the SPEC'2000 Benchmark Suite." IBM Thomas J. Watson Research Center Technical Report RC-21852, October 2000. (ps – pdf)

  20. Suleyman Sair, David R. Kaeli and Jose Fridman. "A Study of Dynamic Branch Prediction for SHARC DSPs." In the Proceedings of the 2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'99), Washington, D.C. (ps)

  21. Suleyman Sair, Guiseppe Olivadoti, David Kaeli and Jose Fridman. "DSPTune : A Performance Evaluation Toolset for the SHARC Signal Processor." In the Proceedings of the 33rd Simulation Symposium, April 2000, Washington D.C.. (pdf)

  22. Suleyman Sair, David R. Kaeli and Waleed Meleis. "A Study of Loop Unrolling for VLIW-based DSPs." In the Proceedings of the 1998 IEEE Workshop on Signal Processing Systems (SiPS '98), Boston, MA. (ps)

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