Power Macromodeling

• Xun Liu and Marios C. Papaefthymiou, HyPE: Hybrid Power Estimation for IP-Based Systems-on-Chip IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) July 2005.
• Xun Liu and Marios C. Papaefthymiou, A Markov chain sequence generator for power macromodeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), July 2004.
• Xun Liu and Marios.C. Papaefthymiou, HyPE: A hybrid power estimation scheme for programmable systems. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), January 2003. [PDF]
• Xun Liu and Marios C. Papaefthymiou, A Markov chain sequence generator for power macromodeling. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), November 2002. [PDF]
• Xun Liu and Marios C. Papaefthymiou, A statistical model of input glitch propagation and its application in power macromodeling. In Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems , August 2002. [PDF]
• Xun Liu, Marios C. Papaefthymiou. Incorporation of input glitches into power macromodeling. In Proceedings of 2002 International Symposium on Circuits and Systems (ISCAS), May 2002. [PDF]
• Xun Liu and Marios Papaefthymiou, A static power estimation methodology for IP-based design. In Proceedings of the 2001 IEEE Conference on Design, Automation, and Test in Europe (DATE), 2001. [PDF]

Timing Analysis and Optimization

• Xun Liu, Marios C. Papaefthymiou, and Eby G. Friedman. Minimizing sensitivity to delay variations in high-performance synchronous circuits. In Proceedings of the 1999 IEEE Conference on Design, Automation, and Test in Europe (DATE), March 1999. [PDF]
• Xun Liu, Marios C. Papaefthymiou, and Eby G. Friedman. Retiming and clock scheduling for digital circuit optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 21, No. 2, February 2002. [PDF]
• Xun Liu, Marios C. Papaefthymiou, and Eby G. Friedman. Maximizing performance by retiming and clock skew scheduling. In Proceedings of the 36th ACM/IEEE Design Automation Conference (DAC), June 1999. [PDF]
• Marios C. Papaefthymiou, Eby G. Friedman, and Xun Liu. Retiming and clock scheduling for high-performance synchronous circuits. In PATMOS '98, Eighth International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), October 1998. [PDF]

VLSI Design

• Xun Liu, Marios C. Papaefthymiou. Design of a 20Mb/s 256-state Viterbi decoder. IEEE Transactions on VLSI (TVLSI), Vol. 11, No. 6, December 2003. [PDF]
• Xun Liu, Marios C. Papaefthymiou. Design of a high-throughput low-power IS95 Viterbi decoder. In Proceedings of the 39th ACM/IEEE Design Automation Conference (DAC), June 2002. [PDF]
• Tongtong Chen, Zhengtao Yu, Yuantao Peng, Yanbin Zhang, Huaiyu Dai, Xun Liu. A MIMO Receiver SoC for CDMA Applications. In SOCC, September 2006.
• Tongtong Chen, Xun Liu. A Case Study of Design Optimization Through Variable Width Selection. In Proceedings of 2009 International Symposium on Circuits and Systems (ISCAS), May 2009.

Practical Repeater Insertion

• Yuantao Peng and Xun Liu. Power Macromodeling of Global Interconnects Considering Practical Repeater Insertion. In GLSVLSI , April 2004.
• Xun Liu, Yuantao Peng, and Marios C. Papaefthymiou. Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? In Proceedings of the 41st ACM/IEEE Design Automation Conference (DAC), June 2004.
• Yuantao Peng and Xun Liu. Global Interconnect Optimization With Simultaneous Macrocell Placement And Repeater Insertion. In SOCC September 2004. [PDF]
• Xun Liu, Yuantao Peng, and Marios C. Papaefthymiou. RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. In Design, Automation, and Test in Europe (DATE), March 2005. [PDF]
• Yuantao Peng and Xun Liu. A Sensitivity Analysis of Low-Power Repeater Insertion. In GLSVLSI , April 2005.
• Yuantao Peng and Xun Liu. Freeze: Engineering a Fast Repeater Insertion Solver for Power Minimization Using the Ellipsoid Method. In the 42nd ACM/IEEE Design Automation Conference (DAC), 2005, to appear. [PDF]
• Yuantao Peng and Xun Liu. RITC: Repeater Insertion with Timing Target Compensation. In ISVLSI , May 2005.
• Xun Liu, Yuantao Peng, and Marios C. Papaefthymiou. Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), to appear.
• Yuantao Peng and Xun Liu. Simple Is Better: Keeping Elmore Delay In Repeater Insertion. In The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC2), September 2005.
• Yuantao Peng and Xun Liu. An Efficient Low-power Repeater Insertion Scheme IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), December 2006.
• Yuantao Peng and Xun Liu. Low-Power Repeater Insertion with Both Delay and Slew Rate Constraints. In the 43rd ACM/IEEE Design Automation Conference (DAC), July 2006.

Rotary Clock Design

• Zhengtao Yu and Xun Liu. Power Analysis of Rotary Clock. In ISVLSI , May 2005.
• Zhengtao Yu and Xun Liu. Power Minimization of Rotary Clock Design. In SOCC, September 2005.
• Zhengtao Yu and Xun Liu. Using Rotary Clock For Low-Power Clock Distribution. In The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC2), September 2005.
• Zhengtao Yu and Xun Liu. Low-Power Rotary Clock Array Design. IEEE Transactions on VLSI (TVLSI), December 2006.
• Zhengtao Yu and Xun Liu. Design of Rotary Clock Based Circuits. In the 44th ACM/IEEE Design Automation Conference (DAC), June 2007.
• Zhengtao Yu and Xun Liu. A 610-MHz FIR Filter Using Rotary Clock Technique. In IEEE Custom Integrated Circuits Conference (CICC), September 2007.
• Zhengtao Yu and Xun Liu. Implementing Multi-phase Resonant Clocking on A Finite Impluse Response Filter. IEEE Transactions on VLSI (TVLSI), Accepted.

High-level Systhesis

• Taemin Kim and Xun Liu. Compatibility path based binding algorithm for interconnection reduction in high level synthesis. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), November 2007.
• Taemin Kim and Xun Liu. Better Than Optimum? Register Reduction Using Idle Pipelined Functional Units. In GLSVLSI, 2009.

Others

• Zhengtao Yu, Marios C. Papaefthymiou and Xun Liu. Skew Spreading for Peak Current Reduction. In GLSVLSI, March 2007.