Research Overview
My research has emphasized the development of efficient algorithms
to design high performance and low power VLSI computing systems.
Currently, I have been working on four projects. The goal of
Design methodologies for low power intellectual property (IP) based
systems project is to develop novel schemes for efficient and
effective power estimation of IP-based VLSI designs. Low power chip
design is becoming an increasingly important focus of VLSI research,
because high power consumption not only limits the application of high
performance chips in mobile battery-dependent systems but also
generates large amounts of heat that reduces chip life, decreases
operating speed, and increases cost due to cooling requirements. Low
power designs require fast and accurate power estimation. In IP-based
design approaches, efficient power tools are particularly important to
ensure short time-to-market and high design quality. There are three
stages in this project. In the first step, new model and method are
designed to characterize the power behaviors of IP circuit blocks. In
the second step, system level power estimation schemes are created to
compute the dissipation of IP-based systems in a very fast and
accurate manner. In the last step, information derived from the second
step is used to redesign the target systems to achieve low power
dissipation without loss of performance. A subtask of this project is
to investigate power minimization schemes for the global interconnects
among IPs
Optimization with accurate clock skew placement project
combines schemes from cell placement and clock skew scheduling
to improve the performance of synchronous circuits.
Practical repeater insertion project develops new schemes for
the implementation of power efficient global interconnects.
Parallel CAD algorithm development project develop techniques
to reduce the runtimes of EDA algorithms and tools using GPUs.